The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode formed over a semiconductive substrate, and spaced apart source and drain electrodes within the substrate between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductive substrate between the source and drain electrodes. Dielectric materials, such as silicon dioxide, are commonly employed to electrically separate the various gate electrodes in the integrated circuit.
Due to the large number of circuit elements and the required complex layout of advanced integrated circuits, the electrical connections of the individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. Such electrical connections are formed in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the intra-level electrical connection, and a plurality of inter-level connections, also referred to as vias, which provide the electrical connection between two neighboring stacked metallization layers. The metal-containing lines and vias may also be commonly referred to as interconnect structures.
Due to the ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, highly conductive metals, such as copper and alloys thereof, in combination with low-k dielectric materials, have become frequently used alternatives in the formation of metallization layers. A plurality of metallization layers stacked on top of each other is employed to realize the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration. For extremely scaled integrated circuits, such as the 32 nm scale and smaller, the signal propagation delay, and thus the operating speed, of the integrated circuit may no longer be limited by the field effect transistors but may be restricted, owing to the increased density of circuit elements requiring an even more increased number of electrical connections, by the close proximity of the metal lines, since the line-to-line capacitance is increased, which is accompanied by the fact that the metal lines have a reduced conductivity due to a reduced cross-sectional area.
During the formation of copper-based metallization layers, a so-called damascene or inlaid technique may be used, due to copper's characteristic resistance to forming volatile etch products when being exposed to well-established anisotropic etch ambients. In addition, copper also may not be deposited with high deposition rates on the basis of well-established deposition techniques usually used for aluminum, such as chemical vapor deposition (CVD). Thus, in the inlaid technique, the dielectric material, such as a silicon oxide, is patterned to receive trenches and/or vias, which are subsequently filled with the copper by an electrochemical deposition technique. Moreover, a barrier layer may be formed on exposed surface portions of the dielectric material prior to filling in the metal, which provides the desired adhesion of the copper to the surrounding dielectric material and also suppresses copper diffusion into sensitive device areas, as copper may readily diffuse in a plurality of dielectric materials, in particular in porous low-k dielectrics.
Manganese has found substantial utility as the barrier layer to be formed prior to filling in the metal. Manganese formed on the exposed surface portions of the silicon oxide dielectric material will form a manganese silicate material during subsequent annealing processes, consuming some space of the silicon oxide dielectric material and thus leaving more volume for the copper to increase the aforementioned copper line conductivity. However, at the bottom of the trenches, where the underlying metallization (copper) layer is exposed, manganese is unable to perform its desired barrier function as the manganese readily diffuses into the copper during the subsequent annealing process. The lack of a barrier material at the underlying metallization layer may result in conductivity problems between the inter-level connection structures and the underlying metallization layer.
As an alternative to a manganese barrier layer, a manganese nitride (MnNx) barrier layer has been proposed. Manganese nitride has a benefit in that it will not diffuse into the underlying metallization layer upon application (and annealing) thereover. However, manganese nitride will not form the manganese silicate material along the exposed surface portions of the silicon oxide dielectric material, thus leaving less room for the metal inter-level connection and consequently a lower conductivity and increased line resistance.
Accordingly, it is desirable to provide improved methods for fabricating integrated circuits using damascene process flows. Additionally, it is desirable to provide such methods that provide increased volume for inter-level metal connection structures while simultaneously preventing electrical conductivity problems between the inter-level connection structures and the underlying metallization layer. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.